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| 1/31 STLC1511 november 2000 this is preliminary information on a new product now in development. details are subject to change without notice. n wide transmit (~80db) and receive (~69db) dynamic range to limit the external filtering requirements for extended loop reach operation n programmable tx gain: 0 -32db in 2db steps n 14-bit d/a converter in transmit path n programmable rx gain: 0 40db in 0.5db steps n 12-bit a/d converter in receive path n integrated phase-locked loop with an externall lc or crystal oscillator n low power: 300mw @ 5.0v n 64-pin tqfp package 1.0 general description the STLC1511 g.lite analog front end (afe) chip implements the analog transceiver functions required in both a central office modem and a customer premise modem. it connects the digital modem chip with the loop driver and hybrid balance circuits. the STLC1511 has been designed with excellent dynam- ic range in order to greatly reduce the external filter- ing requirements at the front end. the afe chip and its companion digital chip along with a loop driver, im- plement the complete g.992.2 dmt modem solution. the STLC1511 transmit path consists of a 14-bit nyquist rate d/a converter, followed by a program- mable gain amplifier (txpga). the transmit gain is programmable from 0 to -32db in 2db steps. the STLC1511 receive path contains a buffer ampli- fier followed by a programmable gain amplifier (rxp- ga), a low pass anti-aliasing filter, and a 12-bit nyquist rate a/d converter. the rxpga is digitally programmable from 0 to 40db in 0.5db steps. 2.0 packaging and pin information 2.1 STLC1511 pin allocation the pinout for the STLC1511 is depicted in figure 1. tqfp64 ordering number: STLC1511 product preview northenlite? g.lite bicmos analog front-end circuit figure 1. STLC1511 pinout 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 vssdige1 rxsout[1] rxsout[0] ck35m vdddig1 digref digclk dtx vdddig2 vssdig2 vdddige1 rxdcinp rxdcinn rxdcon rxdcop rxinp rxinn rxopiinn rxopinp vccrxpga veerxpga qveerx qveedac txdadc1 veedac vccdac vddesd2 vssesd2 veetxpga vcctxpga txon txop qveetx vccpll veepll freq oscnb oscpb oscne qveebias veebias vccbias v3p75v iref50m tqfp64 22 23 24 25 26 60 resetn 61 txsin[0] 62 txsin[1] 63 frmclk 64 vssdig1 adcdc3 adcdc2 adcdc1 vssesd1 vddesd1 17 18 19 20 21 37 36 34 33 35 oscpe vcap vsspll qveepll vddpll 12 13 14 15 16 qveeadc vccadc veeadc enb drx
STLC1511 2/31 2.2 pin description table 1. details the pinout assignment for the STLC1511. the following list gives the different pin types for the STLC1511. n vdd/vcc - 5v power supply n vee/vss - ground supply n do/di - digital output/ digital input n ao/ai/aio - analog output/ analog input/ analog input-output table 1. pin assignement pin # pin name pin type pad type description 1 vdddig1 vdd vddco 5v supply (digital) for adc and dac 2 ck35m di tlcht 35.328mhz serial interface clock input (also used in test mode to test pfd. see table on page 21) 3 digref do bt4cr 35.328/17.644mhz reference for digital asic pll 4 rxsout[0] do bt4cr rx serial data (lsb) output 5 rxsout[1] do bt4cr rx serial data (msb) output 6 vssdige1 vss vsse ground for digital output drivers 7 vssdig2 vss vssco ground supply for digital interface, serial interface 8 vdddige1 vdd vdde 5 v supply for digital output drivers 1 9 vdddig2 vdd vddco 5 v supply for digital interface, serial interface 10 dtx do bt4cr data output for digital interface 11 digclk di tlcht 35.328mhz clock input for digital interface 12 enb di tlcht enable input for digital interface 13 drx di tlcht data input for digital interface 14 veeadc vee vssco ground for adc 15 vccadc vcc vddco 5 v supply for adc 16 qveeadc vee vssco quiet ground for adc circuitry 17 adcdc3 aio ana adc reference decoupling (3.75 v) 0.1uf 18 adcdc2 aio ana adc reference decoupling (2.5 v) 0.1uf 19 adcdc1 aio ana adc reference decoupling (1.25 v) 0.1uf 20 vssesd1 vss vssa ground for esd ring 21 vddesd1 vdd vdda 5 v supply for esd ring 22 rxdcinp ai ana rxpga positive input from dc blocking capacitor 23 rxdcinn ai ana rxpga negative input from dc blocking capacitor 24 rxdcon ao ana rxpga negative output to dc blocking capacitor 25 rxdcop ao ana rxpga positive output to dc blocking capacitor 26 rxinn ai ana rx negative input (ac coupled) 27 rxinp ai ana rx positive input (ac coupled) 3/31 STLC1511 28 rxopinn ai ana rx opamp negative input (must be dc coupled) 29 rxopinp ai ana rx opamp positive input (must be dc coupled) 30 vccrxpga vcc vddco 5v supply for rxpga 31 veerxpga vee vssco ground for rxpga 32 qveerx vee vssco quiet ground for rx circuitry 33 qveepll vee vssco quiet ground for pll circuitry 34 vsspll vss vssco ground for oscillator 2 35 vddpll vdd vddco 5 v supply for oscillator 2 36 vcap ao ana charge pump output to varactor 37 oscpe aio ana oscillator i/o (emitter) 38 oscpb aio ana oscillator i/o (base) 39 oscnb aio ana oscillator i/o (base) 40 oscne aio ana oscillator i/o (emitter) 41 fref ai ana 2.56 mhz pll input reference/ 35.328 mhz clock input 42 veepll vee vssco ground for oscillator 2 43 vccpll vcc vddco 5 v supply for oscillator 2 44 v3p75v aio ana 3.75v output from bandgap to 0.22mf capacitor 45 iref50 m aio ana external resistor for bias current r=2.5v/ 50ma=50kohm 46 vccbias vcc vddco 5v supply for biasing 47 veebias vee vssco ground for biasing 48 qveebias vee vssco quiet ground for bias circuitry 49 qveetx vee vssco quiet ground for tx circuitry 50 txop ao ana tx positive output 51 txon ao ana tx negative output 52 vcctxpga vcc vddco 5v supply for txpga 53 veetxpga vee vssco ground for txpga 54 vddesd2 vdd vdda 5v supply for esd ring 55 vssesd2 vss vssa ground for esd ring 56 vccdac vcc vddco 5v supply for dac 57 veedac vee vssco ground for dac 58 txdadc1 aio ana dac reference (2.5v) 0.1uf table 1. pin assignement pin # pin name pin type pad type description STLC1511 4/31 59 qveedac vee vssco quiet ground for dac circuitry 60 resetn di tlcht resetn for the afe 61 txsin[0] di tlcht tx serial data (lsb) input 62 txsin[1] di tlcht tx serial data (msb) input 63 frmclk do bt4cr tx 4.416mhz frame clock reference output 64 vssdig1 vss vssco ground (digital) for adc and dac <1>hcmos5 guidelines are for 1 pair of power/ground for 4 output drivers (4ma) <2>pins 35 and 43 are both connected to the analog vcc supplying the on chip oscillator. similarly, pins 34 and 42 are connect ed to analog vss for the oscillator. supply line inductance is reduced using two pads for vcc (and vss) in this manner. at the boa rd level, pins 35 and 43 should be connected to analog vcc, and pins 34 and 42 should be connected to analog vss. table 1. pin assignement pin # pin name pin type pad type description 3.0 functional description 3.1 general functional description the STLC1511 consists of the following functional blocks: n transmit signal path n receive signal path n phase lock loop and amplifier for an external oscillator. n bias voltage and current generation n digital interface n serial interface the transmit path contains the 14-bit digital to analog converter (dac) necessary to generate the transmit signal from a 14-bit digital input word. this transmit signal is then scaled by the on chip programmable gain amplifier (txpga) from 0 to -32db in 2db steps. the scaled output signal is then driven off chip to the external filters and power amplifier (pa) which drives the dmt signal to the subscriber loop. the transmit path is fully differential but may be used single ended if both outputs from the txpga are terminated cor- rectly. the receive path contains an optional unity gain buff- er followed by a two stage programmable gain ampli- fier (rxpga), a 1st order low pass anti-aliasing filter, and a 12-bit analog to digital converter (adc). the rxpga consists of two stages and the gain is digitally programmable from 0 to 40db in 0.5db steps. the re- ceive path is fully differential but may be used single ended provided the other input to the rxpga is grounded. the STLC1511 contains the circuits required to con- struct a pll that generates either a 17.644mhz/ 35.328 mhz clock from a 2.56 mhz reference clock when supplied with an external lc or crystal oscilla- tor and tuning circuit. this clock is supplied to the both the transmit and receive converters, and the se- rial interface used to transfer the rx/tx data between the STLC1511 and digital chip. the STLC1511 also has the ability to be driven directly by an external 35.328mhz clock supplied to the fref pin. the bias circuitry contains a bandgap voltage refer- ence from which the converter references and analog ground voltage is generated. this block also gener- ates an accurate current using an external resistor from which all of the STLC1511 circuits are biased. in addition, the bias circuitry also generates a 2.5v ref- erence for the external vco/vcxo components and can be used for other external circuits if necessary. there is a 4 pin serial digital interface ( dtx, drx, digclk, enb ) that loads a one of four 8-bit control register that controls all the programmable features on the STLC1511. refer to digital interface and memory map on page 20 for more information on the programmability of the afe. to facilitate data transfer between the STLC1511 and the digital asic (stlc1510), a 2-bit wide serial interface for the transmit path and a 2-bit wide serial interface for the receive path is incorporated into the afe. this interface consists of two transmit pins ( tx- sin[0:1] ), two receive pins ( rxsout[1:0] ), and the necessary control signals ( frmclk, ck35m ) to transmit the required data. for more information see serial interface on page 18. 5/31 STLC1511 figure 2. the block diagram of the STLC1511 3.2 receive path specifications note: the first stage of the rxpga provides a coarse gain of 0/20db with a differential input or 6/26db with a single ended input. the second stage implements a programmable gain from 0db to 20db in 0.5db steps. 12 14 d igital i/f serial i/f bandgap/ bias gen 14-bit 12-bit adc dac 4.416m 4.416m 35.328m/ 5 8/4 69 2.56m /35.328m 2.56m 35.328m (external clock mode) (o scillator mode) digclk enb drx rxinn rxinp rxdcop rxdcon rxdcip rxdcin txsin[1:0] frmclk rxsout[1:0] ck35m v3p5v iref50u 0.22uf 50k txop txon fref vcap 2 2 resetn ex t e rn al resonator g oscne oscpe oscpb oscnb dig i/f dtx 90 digref 17.622m rxopinp rxopinn + - 2/3/4/8 pfd cp + - g=1 fp=2mhz fp=2mhz adcdc1 adcdc2 adcdc3 txdadc1 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf + - + -+ - shaded blocks are only usabe when the pll is active. crystal based external resonator for the cpe mode, lc based resonator for the co oscillator mode. 35.328 mhz external reference in co external clock mode. STLC1511 6/31 table 2. receive path specifications unless otherwise noted, typical specifications apply for vcc=5.0volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments 1 st stage absolute gain 1 2 diff in to diff out 3 d = 00 d = 01 single ended in to diff out 3 d = 10 d = 11 0 20 6 26 db db where d is the binary value in b[7:6] of the control word. includes vcc, temperature, process, and frequency variation. 2 nd stage absolute gain 1 2 diff in to diff out 4 0 =< d =< 40 d > 40 (0.5 d) - 1.8 18.2 (0.5 d) 20 (0.5 d) + 0.8 20.8 db where d is the binary value in b[5:0] of the control word. includes vcc, temperature, process, and frequency variation. relative gain accuracy 5 (relative to ideal gain of 0.5db per lsb change.) -0.4 +0.4 db for more than a 1lsb change in the control word. assumes a fixed vcc, temperature, and frequency. gain variation with temperature 6 -0.3 +0.3 db for a fixed vcc and frequency f (30khz =< f =< 540khz) relative to 27 o c. gain variation with supply voltage 7 -0.1 +0.1 db for a fixed frequency f. (30khz =< f =< 540khz) and fixed temperature relative to vcc=5.0v. gain variation with frequency 8 30khz =< f =< 120khz 155khz =< f =< 540khz -1.0 -1.0 0 0 db for a fixed vcc and temperature. relative to 30khz relative to 155khz gain step size for all steps except step 19.5 to 20db (differential) or step 25.5 to 26db (single ended) for step 19.5 to 20db (differential) or step 25.5 to 26db (single ended) 0.4 0.3 0.5 0.5 0.6 0.7 db db for a 1 lsb change in the control word at a fixed frequency f. (30khz =< f =< 540khz) 7/31 STLC1511 input referred noise 9 10 11 12 at g=0db at g=max 13 at g=0db at g=max 11 250 15 250 20 252 19 252 27 spot noise @30khz measured single ended at rxinp or rxinn spot noise @30khz measured differentially at rxinp/n input referred noise 9 10 11 at g=0db at g=max 11 250 20 252 27 spot noise @30khz measured differentially at rxdcinp/n op amp input referred noise 9 10 11 10 15 spot noise @30khz measured differentially at rxopinp/n output signal to distortion ratio two tone (ate testing) 14 ds multi tone 15 30khz =< f =< 120khz 155khz =< f =< 540khz us multi-tone 16 30khz =< f =< 120khz 155khz =< f =< 540khz 60 63 63 63 63 66 69 69 69 69 db for all rxpga gain. measured at output of adc input impedance @pins rxopinp/n @ pins rxinp/n @ pins rxdcip/n 250 1 1 1000 19 10 kw rx opamp input pins rx pga input pins rx ac coupling pins dc offset at output 15 mv measured at output of adc max input signal level single ended differential 1.2 2.4 vpe ak vpe ak single-ended input differential input measured at any input (rxinp/n, rxopinp/n, or rxdcinp/n) settling time 17 300 nsec time for pga to settle to 3t accuracy after a change in the control word indicated by enb going high. unless otherwise noted, typical specifications apply for vcc=5.0volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments nv hz ----------- nv hz ----------- nv hz ----------- table 2. receive path specifications STLC1511 8/31 power up time 18 rx @ ds 19 rx @ us 20 100 530 mse c time to meet output snr requirement <1>for the purposes of this specification, a gain of 1 or 0db is defined as the ratio of the full scale adc output word to the input voltage at rxinp/rxinn when the input to the rx path is at 2.4vp differential measured between rxinp and rxinn. <2>for g.lite the STLC1511 will support both co and cpe applications. as such it needs to support rates from 30khz to 120khz (c o receive band) and 155khz to 540khz (cpe receive band). <3>first stage gain is measured from rxinp/rxinn (differential input) to rxop/rxon (differential output). note that the gain fr om input to output can be adjusted for single ended input or differential input so that the output signal level at the output of t he first stage of the pga is at full scale. for a single ended input, the unused input, either rxinp or rxinn must be ac coupled to grou nd. <4>second stage gain is measured from rxdcinp/rxdcinn (differential input) to the output of the adc. <5>will be tested at vcc=5.0v, 27 o c, and f=275khz. <6>will be tested at vcc=5.0v and f=275khz. <7>will be tested at 27 o c and f=275khz. <8>will be tested at vcc=5.0v and 27 o c. <9>due to 1/f component, the spot noise is maximum at 30khz over the bands of interest (us and ds). <10>noise voltage is specified as the noise spectral density ( e n ) at the input. conversion to power spectral density is as follows <11>input referred noise assumes that there is a 7db cut in the first band of aliased noise which falls into the dmt frequencie s and that higher order aliases are negligible. for example, the single ended input referred noise for the maximum gain setting of 40 db is calculated as follows: in general, the single ended input referred noise can be calculated as follows: where g1 and g2 are the gains of the first and second stages of the rxpga respectively. note that the assumption of a 7db cut on the aliased noise is also used in the above formula and that all other higher order noise is sufficiently suppressed. <12>note that the rx path noise at 0db gain is dominated by the quantization noise of the adc and as such there is very little process, vcc, or temperature dependency and the variation from typical to maximum noise is only due to the rx pga. <13>at maximum gain pga and rx input opamp noise are the dominant contributors. <14>two tone distortion is measured with two sinewaves with each sinewave at an amplitude of 1/2 full scale. tone one is at f1=400khz and tone two is at f2=500khz. the two tone distortion requirement is measured from the rms voltage of a single signal tone to the peak rms voltage of the distortion products. <15>a multi-tone sine wave is used for the ds multi-tone test. (the multi-tone signal will be 89 sinewaves equally spaced from 36*4.3125khz to 125*4.3125khz with a peak-to-rms ratio of 5.3v/v and an rms voltage equal to 1/5.3 of the peak full scale ran ge of the pga.) multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <16>a multi-tone sine wave is used for the us multi-tone test. (the multi-tone signal will be 22 sinewaves equally spaced from 7*4.3125khz to 28*4.3125khz with a peak-to-rms ratio of 5.3v/v and an rms voltage equal to 1/5.3 of the peak full scale range of the pga.) multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <17>the 1t settling time is roughly equivalent to the unity gain frequency of the pga block. <18>the power up time is the time it takes the power up transient to dissipate such that the output snr specification is met. t his time is dominated by the coupling capacitors at pins rxinp/n and rxdcip/n . unless otherwise noted, typical specifications apply for vcc=5.0volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments psd 10 en 2 100 --------- - 1000 ? ?? log = en 1 1 10 720 ----------------- + ? ?? 17nv hz () 2 17nv hz 10 20 20 ------------------------------ ? ? ?? 2 + ? ? ?? 250nv hz 10 40 20 --------------------------------- - ? ? ?? 2 + = en 1 1 10 710 ----------------- + ? ?? 17nv hz () 2 17nv hz 10 g1 20 ------------------------------ ? ? ?? 2 + ? ? ?? 250nv hz 10 g1 g2 + () 20 ------------------------------------- ? ? ?? 2 + = table 2. receive path specifications 9/31 STLC1511 3.3 transmit path specifications <19>minimum ds frequency is 36*4.3125khz=155.25khz and as such the coupling capacitors between rxinp/n and rxdcip/n must be such that the high pass pole is ~15khz (typical). with a 1kw minimum input impedance at rxdcip/n this gives a capacitor value of about 10nf. this gives a 1t settling time of 10ms.to guarantee 12-bit performance a minimum of 10t settling gives 100m s. <20>minimum ds frequency is 7*4.3125khz=30.1875khz and as such the coupling capacitors between rxinp/n and rxdcip/n must be such that the high pass pole is ~3khz (typical). with a 1kw minimum input impedance at rxdcip/n this gives a capacitor value of about 53nf. this gives a 1t settling time of 53ms.to guarantee 12-bit performance a minimum of 10t settling gives 530m s. table 3. transmit path specifications unless otherwise noted, typical specifications apply for vcc=5 volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments absolute gain 1 2 0 =< d =< 16 d > 16 -(2 d) - 1.8 -33.8 -(2 d) -32.0 -(2 d) - 1.0 -31.0 db where d is the binary value in b[11:7] of the control word. includes vcc, temperature, process, and frequency variation. gain step size 1.8 2.0 2.2 db for a 1 lsb change in the control word at a fixed frequency f (30khz =< f =< 540khz) relative gain accuracy 3 (relative to ideal gain of 2db per step.) -0.4 +0.4 db for more than a 1lsb change in the control word. assumes a fixed vcc, temperature, and frequency. gain variation with temperature 4 -0.3 0.3 db for a fixed vcc and frequency f (30khz =< f =< 540khz) relative to 27 o c. gain variation with supply voltage 5 -0.1 0.1 db for a fixed frequency f. (30khz =< f =< 540khz) and fixed temperature relative to vcc=5.0v. gain variation with frequency 6 30khz =< f =< 120khz 155khz =< f =< 540khz -0.6 -1.0 0 0 db for a fixed vcc and temperature. relative to 30khz relative to 155khz STLC1511 10/31 output signal to distortion ratio two tone 7 ds multi-tone 8 30khz =< f =< 120khz 155khz =< f =< 540khz us multi-tone 9 30khz =< f =< 120khz 155khz =< f =< 540khz 75 78 76 78 78 81 84 82 84 84 db for all txpga gains. measured differentially at txop/n output referred noise voltage 10 11 12 txpga gain = 0db 30khz =< f =< 120khz 155khz =< f =< 540khz txpga gain = min 30khz =< f =< 120khz 155khz =< f =< 540khz 80 80 30 30 100 100 40 40 measured differentially at txop/n output signal to noise and distortion ratio (ds) 13 14 txpga gain = 0db 30khz =< f =< 120khz 155khz =< f =< 540khz txpga gain = min 30khz =< f =< 120khz 155khz =< f =< 540khz 74 73 53 53 80 79 59 59 db measured differentially at txop/n output signal to noise and distortion ratio (us) 15 13 txpga gain = 0db 30khz =< f =< 120khz 155khz =< f =< 540khz txpga gain = min 30khz =< f =< 120khz 155khz =< f =< 540khz 76 76 55 55 82 82 61 61 db measured differentially at txop/n out of band noise 72 band from 550khz - 2.2 mhz (f s /2) maximum output signal @txop/n 2.4 vp differential output load resistance @ pin txop/n 500 w per output to 2.5v load capacitance @ pin txop/ n 10 pf per output to 2.5v table 3. transmit path specifications unless otherwise noted, typical specifications apply for vcc=5 volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments nv hz ----------- nv hz ----------- 11/31 STLC1511 settling time 16 300 nsec time for pga to settle to 3t accuracy after a change in the control word indicated by enb going high. <1>for the purposes of this specification, a gain of 1v/v (i.e. 0db) is defined as the ratio of the full scale dac input word t o the output voltage at txop/txon when the output from the tx path is at 2.4vp differential measured between txop and txon. <2>for g.lite the STLC1511 will support both co and cpe applications. as such it needs to support rates from 30khz to 120khz (cpe transmit band) and 155khz to 540khz (co transmit band). 275khz is roughly in the middle of the required frequency range. <3>will be tested at vcc=5.0v, 27 o c, and f=275khz. <4>will be tested at vcc=5.0v and f=275khz. <5>will be tested at 27 o c and f=275khz. <6>will be tested at vcc=5.0v and 27 o c. <7>two tone distortion is measured with two sinewaves with each sinewave at an amplitude of 1/2 full scale. tone one is at f1=400khz and tone two is at f2=500khz. the two tone distortion requirement is measured from the rms voltage of a single signal tone to the peak rms voltage of the distortion products. <8>a multi-tone sine wave is used for the ds multi-tone test. (the multi-tone signal will be 89 sinewaves equally spaced from 36*4.3125khz to 125*4.3125khz with a peak-to-rms ratio of 5.3v/v and an rms voltage equal to 1/5.3 of the peak full scale ran ge of the pga.) multi-tone measures the difference between the rms voltage of a single tone at the output to the rms voltage of th e peak distortion product at the output in the band of interest. <9>a multi-tone sine wave is used for the us multi-tone test. (the multi-tone signal will be 21 sinewaves equally spaced from 7*4.3125khz to 28*4.3125khz with a peak-to-rms ratio of 5.3v/v and an rms voltage equal to 1/5.3 of the peak full scale range of the pga.) multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <10>noise voltage is specified as the noise spectral density ( e n ) at the output. conversion to power spectral density is as follows: <11>the output referred noise voltage for the STLC1511 can be calculated as follows: where g is the gain of the txpga expressed in db. <12>the output referred noise of the tx path at the 0db gain setting is mainly due to the output referred noise of the dac ampl ified by 5.3db to the output of the chip. the dac noise itself is made up of roughly equal contributions between quantization noise a nd thermal noise. it is only the thermal noise portion which will significantly change between a typical and worst case device. <13>the sndr is the ratio of psd of the signal to the psd of the noise plus distortion. the input for this test is as described in h above scaled by the gain to produce a full scale output signal. <14>the effective noise plus distortion floor can be calculated from the sndr based on the psd of the output signal . so that for g=0, the effective noise plus distortion floor will be at -52.7dbm/hz - 74db = -126.7dbm/hz and for g=max, the floo r is at -52.7dbm/hz -32db (cutback) - 53db = -137.7dbm/hz <15>the sndr is the ratio of psd of the signal to the psd of the noise plus distortion. the input for this test is as described in i above scaled by the gain to produce a full scale output signal. <16>1t settling time is roughly equivalent to the unity gain frequency of the pga block. table 3. transmit path specifications unless otherwise noted, typical specifications apply for vcc=5 volts, temperature=2 7 c, nominal process and current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105 c, and worst case process. description min typ max units comments psd 10 en 2 100 --------- - 1000 ? ?? log = en 40nv hz () 2 10 g5.3 + () 20 50nv hz () 2 + = psd 10 2.4 5.3 540khz 155khz C () () 2 100 -------------------------------------------------------------------------------------------- - 1000 ? ?? log 52.7dbm hz C == STLC1511 12/31 3.4 phase lock loop the STLC1511 has been intended for use in either the central office application (co) using an external clock of 35.328mhz, in the central office application using an external 2.56mhz clock and on-ship pll , or in a customer premise equipment application (cpe). in the co application (external clock mode), the ref- erence clock used for the converters and internally in the STLC1511 is provided by an external reference. in the co application (oscillator mode), the STLC1511 provides the ability to drive a lc oscillator and generate the require clocks using an on-chip pll. in the customer premise equipment (cpe) ap- plication, the STLC1511 provides the crystal driver for use with a external crystal and feedback network. in the cpe application the tuning signal must be pro- vided by the digital modem asic (stlc1510). while the above descriptions highlight the intended applications, the STLC1511 also has the flexibility to provide a pll function when used with a different ref- erence frequency and external 35.328mhz crystal. table 4 highlights the different pll modes for the STLC1511. 3.4.1 central office (external clock mode) in co external clock mode the 35.328mhz refer- ence clock on pin fref is divided down and used in both the tx and rx converters. in this mode of oper- ation, the pll and oscillator driver are powered down. external clock mode is selected by setting b5:b0 of register afe control 4 to 000000. see section 3.7 for more information. 3.4.2 central office (oscillator mode) in oscillator mode the 2.56mhz reference clock on pin fref is used as the reference clock for the STLC1511 pll. this clock is used to lock the lc os- cillator frequency to 88.32mhz which is further divid- ed down to provide the sampling clocks to both the tx and rx converters and passed to the digital asic stlc1510 as its pll reference on the pin digref . the clock supplied to the digital asic stlc1510 via digref is running at a rate of 17.664mhz in this mode. details the co pll and oscillator performance when connected as shown in figure 3, "co frequency vs. tuning voltage". co oscillator mode is selected by setting b5:b0 in register afe control 5 to 001001. see section "digital interface and memory map" on page 20 for more information. table 4. pll application modes 1 description fref freq mhz digref freq mhz pll active? lc osc freq mhz xtal freq mhz afe control 5 [b5:b0] co external clock mode 2 35.328 35.328 no n/a n/a 000000 co oscillator mode 2.56 17.664 yes 88.32 n/a 001001 cpe mode n/a 35.328 no n/a 35.328 000110 pll misc. 1 1.536 35.328 yes n/a 35.328 011110 pll misc. 2 2.048 35.328 yes n/a 35.328 101110 pll misc. 3 4.096 35.328 yes n/a 35.328 111110 <1>presently only applications described in this table are supported. <2>the clock jitter specification for an externally supplied dac or adc clock (on pins fref when in co external clock mode) is the same as the jitter specification for the pll. 13/31 STLC1511 table 5. co pll specifications unless otherwise noted, typical specifications apply for vcc=5.0 v, temperature=25c, nominal process and bias current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105c, and worst case process. description min typ max units comments reference clock frequency 2.56 mhz on pin fref output clock frequency 17.644 mhz at pin digref lc frequency tuning range e 84 88.32 94 mhz assumes 2% capacitors. oscillator signal level 200 500 mvp power up time 200 msec vco gain vco gain (lc) 5.0 5.4 6 mhz/v see caption figure 4 on page 14 charge pump current 180 200 220 ma input impedance @oscpb and oscnb 1 <1>input and output impedance measured with 50kw from oscpb to vcc and oscnb to vcc see title 3 3.4.3 on page 16 output impedance @oscpe and oscne a see title 3 3.4.3 on page 16 co phase noise at f s 2 5khz offset 10khz offset 20khz offset 30khz offset 100khz offset 200khz offset 300khz offset 400khz offset 500khz offset <2>for inband noise, phase noise at multiples of 4.3125khz will rms add to degrade the inband snr. similarly, for out of band s ignals, phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the snr. for example, noise contributions on carriers from 34 to 127 will rms add to degrade the snr on the edge of the us band (carrier 26). 89 91 97 101 120 129 133 137 141 dbc/hz phase noise at digref output (i.e. 17.664mhz) in co oscillator mode. STLC1511 14/31 figure 3. co frequency vs. tuning voltage figure 4. co frequency vs. tuning voltage afe vcc i oscne oscnb oscpb oscpe vcc 2.5v i ce ce c p c p vcap charge pump osc_outp osc_outn l 1n 1n cv l ce=100pf c p=27 pf l=56nh cv=10pf rb=4k w rx=1m w 15/31 STLC1511 figure 5. oscillator input impedence figure 6. oscillator output impedence STLC1511 16/31 3.4.3 customer premise equipment in cpe mode, the STLC1511 provides the amplifier required to power the off-chip crystal oscillator. the crystal oscillator runs at a frequency of 35.328 mhz (series resonant) which is further divided down to provide the sampling clocks to both the tx and rx converters and passed to the stlc1510 as its pll reference on the pin digref . note that in cpe mode, neither the pll or the pin fref is used ( fref should be connected to either vdd or vss) and that the tuing for the external oscillator is generated on the stlc1510. the following table details the cpe oscillator perfor- mance when connected as shown in figure 3. on page 14. cpe mode is selected by setting b5:b0 in register afe control 5 to 001110. see section "digital interface and memory map" on page 20 for more information. note the reference design provided is based on a reeves hoffman fundamental mode at cut crystal at 35.328mhz.(crystal accuracy@+/-50ppm (+/-15ppm calibration tolerance, +/-15ppm 10 year aging, +/-20 ppm temperature variation, rs@15 w max, cm@15ff max, and co@3.5pf typ (assumes a hc49/43 package).) table 6. cpe pll specifications unless otherwise noted, typical specifications apply for vcc=5.0 v, temperature = 25c, nominal process and bias current. maximum and minimum performance is with vcc 5%, -40 =< t junction =< 105c, and worst case process. description min typ max units comments output clock frequency 35.328 mhz at pin digref crystal accuracy 1 2 -50 +50 ppm crystal accuracy for cpe. crystal frequency tuning range 2 3 -125 +125 ppm occurs at cpe. assumes co is free running oscillator signal level 200 500 mvp power up time 5 10 msec vco gain vcxo gain (crystal) 1.4 1.6 1.7 khz/v see title 2 3.5 on page 18 input impedance @oscpb and oscnb 4 see title 3 3.4.3 on page 16 output impedance @oscpe and oscne 4 see title 3 3.4.3 on page 16 cpe phase noise at f s 5 10hz offset 20hz offset 40hz offset 60hz offset 80hz offset 100hz offset 200hz offset 400hz offset 600hz offset 800hz offset 1000hz offset -51.9 -57.9 -63.9 -67.5 -69.9 -71.9 -77.9 -83.9 -87.5 -89.9 -91.9 dbc/hz phase noise at digref output (i.e. 35.328mhz) in cpe mode. <1>for the cpe side a crystal oscillator will be used. <2>50ppm accuracy is divided as 15ppm for manufacture, 15ppm for 10 year drift, and 20ppm for temperature variation. <3>worst case for tuning is when co is not locked and cpe must retime from co. nominally the tuning range for the co is 50ppm, so that if the co is free running, the cpe must tune over the co inaccuracy and the cpe crystal inaccuracy as well. <4>input and output impedance measured with 50kw from oscpb to vcc and oscnb to vcc <5>for inband noise, phase noise at multiples of 4.3125khz will rms add to degrade the inband snr. similarly, for out of band s ignals, phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the snr. for example, noise contributions on carriers from 34 to 127 will rms add to degrade the snr on the edge of the us band (carrier 26). 17/31 STLC1511 figure 7. typical cpe oscillator configuration figure 8. cpe frequency vs. tuning voltage afe vcc 2.5v i oscne oscnb oscpb oscpe vcc i ce ce c p c p vcap osc_outp osc_outn cpe asic digital ds clock recovery 5v 5v current output cv lm cm rm co cm=15ff c o=3.5 pf rm=15 w crystal model ce=180pf c p=82 pf cv=20pf rb=4k w rx=1m w STLC1511 18/31 3.5 reference voltages 3.6 serial interface the serial interface on the afe provides for transmis- sion of transmit and receive data between the STLC1511 and digital modem asic. this is accom- plished with a two bit wide data stream in each direc- tion plus the appropriate clocks. the data for the transmit path is input to the afe on the txsin[1:0] pins and the data for the receive path is output on the rxsout[1:0] pins. the serial interface also consists of a 35.328mhz clock ( ck35m ) which is generated in the stlc1510 and is used to retime the tx data sent to the STLC1511. it is also used in the STLC1511 to retime the rx data before it is sent to the digital chip. a 4.416mhz pulse is also output from the STLC1511. this pulse on pin frmclk is used to indicate the start of the output and input data words. the align- ment of the data to the frmclk signal is shown be- low. a diagram of this interface is show in figure 11. note the msb of each of the 8-bit registers is trans- ferred first (msb = b15/ b7.) note that the data word used by the converters is in 2s complement notation. table 7. reference voltages/currents unless otherwise noted, typical specifications apply for vcc = 5.0 v, temperature=25c, nominal process and bias current. maximum and minimum performance is with vcc 5%, -40 = STLC1511 20/31 figure 10. clip indicator output. bit 0 in the afe status register is also set to high when a clip occurs. this bit can be disabled via the control interface, see table 8 on page 21 for more details. this bit is cleared on read. for more informa- tion see "digital interface and memory map" on page 20. 3.6.2 tx loop back when bit b1 of register 011 (afe control 4) is as- serted the data received on the txsin[1:0] pins is converted to parallel and then sent directly to both the dac and the rx parallel data input replacing the usu- al data from the adc. this allows a loop back to the input tx data from txsin[1:0] to the rxsout[1:0] to help the testability of the serial interface. 3.7 digital interface and memory map all parametric specifications in table 2 on page 6 and table 3 on page 9 are guaranteed assuming that the digital interface is inactive. all parametric specifications in table 2 and table 3 are guaranteed assuming that the digital interface is inactive. the digital interface operates at a rate of 35.328 mhz. the companion dsp chip, stlc1510, sources the 35.328 mhz clock used by the afe. to minimize the impact of digital noise on the STLC1511, this supplied clock is gated, and is only enabled during data transfers and during reset. the clock does not need to be present in order to re- set the chip. the processor interface consists of four pins: 1) the 35.328 mhz gated clock (digclk); 2) a data in port for data transfers (drx); a data out pin for data trans- fer (dtx); and 4) a chip select pin (enb). there are a total of 12 bits which are serially transmit- ted between the stlc1510 and afe during data transfers. the gated clock lasts for a duration of 12 clock cycles. this 12 cycle interaction consists of a r/ w bit, a 3 bit address, and a 8 bit data word. the format for this serial transaction is given below in figure 11. ck35m frmclk rxsout[0] rxsout[1] b[15:8]=7f b[7:0]=ff rxsout[0] rxsout[1] b[15:8]=80 b[7:0]=00 positive clip negative clip figure 11. digital interface timing diagram digck enb (35mhz) data[b7:b0] for write access address r/w drx [a2:a0] data[b7:b0] for read access dtx 21/31 STLC1511 during a transaction, the first bit sent to the afe de- termines the type of transaction, r/w =1 corre- sponds to a read transaction while r/w =0 corresponds to a write transaction. the next three bits, address[a2:a0], determine which of the 8 afe registers will be accessed (table 8). this is followed by the 8-bit data word. in both read and write transactions, bit 0 ( lsb ) of the serially transferred 8-bit word is clocked from the data source first (the data source being the external dsp during write transactions; the STLC1511 during read transactions). the definition of these fields within the 8-bit word is outlined below in table 8 and in the detailed register maps following. when the voltage on the resetn pin is low, the bits in the control register will be reset as per defined in the detailed register maps. for a write operation, the data on the drx pin is latched into the STLC1511 on the negative edge of the digclk signal. the data should change state on the positive edge of the clock. for a read operation, the data on the dtx pin is out- put on the positive edge of the clock on pin digclk . table 8. afe register map summary addr [a2:a0] name d7 d6 d5 d4 d3 d2 d1 d0 type 000 STLC1511 control 1 (rx pga gain) rx pga gain rw 001 STLC1511 control 2 (tx pga gain) not used tx pga gain rw 010 STLC1511 control 3 (power down reg) not used rx opa mp pow er dow n not use d rx pow er dow n tx pow er dow n rw 011 STLC1511 control 4 (misc. control) not use d div output (test mode) pll pfd inpu t sel tx loo p back clip indic ator ena ble rw 100 afe control 5 (pll control) not use d dig- ref ena ble fref mode pll mod e osc mod e 1 clock source control r/w 101 not used not used 110 not used not used 111 afe status not used clip stat us r <1>presently there is no difference in the oscillator driver between oscillator mode and cpe modes so this bit is unused. howe ver, it may be required in the future and should be programmed correctly in case needed. STLC1511 22/31 table 9. detailed register map: afe control byte 1 title: afe control 1 (rx pga gain) label: rx gain access type: r/w address: 000 bits used: 8 description: rx pga gain setting bit label bit(s) value bit description reset rx gain b5-b0 0?d?40 d?40 gain=d*0.5 db gain=20 db 000000 rx gain msb b7-b6 00 01 10 11 gain=0 db gain=20 db gain=6 db gain=26 db 0 table 10. detailed register map: afe control byte 2 title: afe control 2 (tx pga gain) label: tx gain access type: r/w address: 001 bits used: 5 description: tx pga gain setting bit label bit(s) value bit description reset tx gain b4-b0 0?d?16 d?16 gain= -d*2 db gain=-32 db 00000 not used b7-b5 000 table 11. detailed register map: afe control 3 title: afe control 3 (power down reg) label: power down access type: r/w address: 010 bits used: 3 description: power down register bit label bit(s) value bit description reset tx power down 1 b0 0 1 power up transmit path power down transmit path 1 rx power down 2 b1 0 1 power up receive path power down receive path 1 not used b2 0 23/31 STLC1511 rx opamp power down b3 0 1 power up rxpga power down rxpga 1 not used b7-b4 0 <1>during power down the tx serial interface is also disabled and txsclk is tristated. <2>during power down the rx serial interface is also disabled and rxsclk and rxsout[1:0] are tristated table 12. detailed register map: afe control 4 title: afe control 4 (misc. control) label: misc control access type: r/w address: 011 bits used: 5 description: mode control/misc. bit label bit(s) value bit description reset clip indicator enable b0 0 1 clip indicator disabled clip indicator enabled 1 tx loop back b1 0 1 normal operation test mode. tx data sent to serial i/f is muxed to rx input and trasmitted via the serial i/f 0 pll phase/freq input select (test mode) b2 0 1 source of pll phase-frequency detector feedback input. output of feedback dividers. signal on fref is sent directly to pfd (ref input) and signal on pin ck35m is sent directly to pfd (vco input). 0 div output (test mode only) b3-b4 00 01 10 11 normal operation output of div69 counter is output to digref pin output of div2/3/4/8 counter is output to digref pin output of div5 counter is output to digref pin 0 not used b7-b5 000 table 11. detailed register map: afe control 3 title: afe control 3 (power down reg) label: power down access type: r/w address: 010 bits used: 3 description: power down register bit label bit(s) value bit description reset STLC1511 24/31 table 13. detailed register map: afe control 5 title: afe control 5 (pll control) label: pll control access type: r/w address: 100 bits used: 7 description: pll control register bit label bit(s) value bit description reset clock source control b0-b1 00 01 10 11 (co external clock mode.) output of clock selection mux is from fref pin. this state also powers down the pll and oscillator driver. (co oscillator mode.) output of clock selection mux is from output of divide by 5. (cpe mode). output of clock selection mux is from output of oscillator driver. (other cpe mode). output of clock selection mux is from output of oscillator driver. 00 osc mode 1 b2 0 1 (co oscillator mode.) afe is configured to drive external 88.32mhz lc oscillator. (cpe mode.) afe is configured to drive external 35.328mhz crystal oscillator. 1 pll mode b3 0 1 pll active (pfd,cp active) pll inactive (pfd,cp powered down) 0 fref mode 2 b5-b4 00 01 10 11 fref frequency is 2.56mhz fref frequency is 1.536mhz fref frequency is 2.048mhz fref frequency is 4.096mhz 00 digref enable b6 0 1 digref output pin tristated digref output pin active 1 reserved b7 0 <1>presently there is no difference in the oscillator driver between co oscillator and cpe modes so this bit is unused. howeve r, it may be required in the future and should be programmed correctly in case needed. <2>for fref at 2.56mhz (b5:b4 = 00), the compare frequency for the pll is at 1.28mhz. for all other fref modes the compare frequency is at 512khz. 25/31 STLC1511 table 14. detailed register map: not used title: afe control 6 (misc control 2) label: misc control 2 access type: r/w address: 101 bits used: 0 description: bit label bit(s) value bit description reset not used b7-b0 00000000 table 15. detailed register map: not used title: not used label: access type: r/w address: 110 bits used: 0 description: bit label bit(s) value bit description reset not used b7-b0 00000000 table 16. detailed register map: afe status title: afe status label: afe status access type: r address: 111 bits used: 2 description: afe read only status bit label bit(s) value bit description reset clip status? b0 0 1 a/d clip not detected a/d clip detected 0 not used b7-b2 000000 STLC1511 26/31 3.8 timing table 17. describes the timing relationships between important signals. 3.9 power up reset when the voltage on the resetn pin is low the bits in the control register will be reset as per the detailed reg- ister maps in digital interface and memory map on page 20. in addition, digital output pins, dtx , frmclk , and rxsout[1:0] are high impedance. the other digital outputs are always as defined in table 1 on page 2. table 17. timing symbol parameter spec min typ 1 <1>load on all output pads assumed to be < 25pf.this gives a delay through the tlcht pad of approximately 5ns. spec max unit s t senb enb falling to digclk rising 1 5 ns t henb enb rising to digclk falling 1 5 ns t sdrx data in valid to digclk falling 2 5 ns t hdrx digclk falling to data in hold 2 5 ns t ddtx digclk rising to data out valid 5 10 ns t sck35 txsin[1:0] valid to ck35m falling 2 5 ns t hck35 ck35m falling to txsin[1:0] hold 2 5 ns t drx ck35m rising to rxsout[1:0] valid 5 10 ns t dfc ck35m rising to frmclk valid 5 10 ns t ddrck35 digref rising to ck35m rising 10 12 20 ns t rdigref digref rise time (20% to 80%) 1 2 3 ns t fdigref digref fall time (80% to 20%) 1 2 3 ns 27/31 STLC1511 4.0 package information, supply ratings, and operating environment 4.1 the thermal impedance the thermal impedance of the package is about 64 c/w for the following conditions comment on reliability: the maximum continuous junction temperature for this part while meeting 20 year reliability is 125 c. 4.2 environmental conditions 4.3 power supply input limits table 21. defines the maximum and minimum power supply requirements to meet specifications as outlined in section 3.2 and 3.3. table 18. board assumptions: pc board 6 layer, 1oz copper ambient temperature 85 0 c air flow natural convection power dissipation 300mw table 19. board assumptions: pc board 6 layer, 1oz copper ambient temperature 85 0 c air flow natural convection power dissipation 300mw table 20. environment conditions t a long-term (continuous) -40 to +80 0 c t a short-term 1 <1>short-term is defined as no greater than 96 consecutive hours and 15 days per year. -40 to +85 0 c table 21. power supply limits parameter limits unit conditions min typ max 1 positive supply voltage 4.75 5 5.25 volts STLC1511 28/31 4.4 power supply noise 4.5 absolute maximum ratings the following table describes the maximum and minimum voltage ratings tx powered up co oscillator mode co external clock mode cpe mode tx powered down co oscillator mode co external clock mode cpe mode 65 60 65 41 36 41 71 66 71 45 39 45 ma includes 4ma for digital supplies and digital i/o tx powered up co oscillator mode co external clock mode cpe mode tx powered down co oscillator mode co external clock mode cpe mode 325 300 325 200 175 200 373 347 373 237 205 237 mw includes 20mw for digital supplies and digital i/o <1>maximum current assumes a 7% increase due to process/temperature/vcc plus the variation in the external 50k resistor (assume d 2%) connected to iref50u. for this table the total variation is assumed at 9%. table 22. power supply noise noise band maximum 5v supply noise spectral density max 5v supply noise (over noise band) 30khz < f < 112khz 1.4 m vrms/rthz @ 112khz, rising 6db per octave for decreasing frequency 1.0mvrms 146khz < f < 547khz 1.0 m vrms/rthz @ 146khz, dropping 6db per octave to 0.25 m vrms/rthz @ 547khz 0.30mvrms table 23. maximum and minimum voltage ratings pin maximum minimum all vcc pins 6.5v -0.5v all other pins vcc+0.4 -0.4 table 21. power supply limits parameter limits unit conditions min typ max 1 29/31 STLC1511 4.6 pin dc electrical specification bt4cr is a cmos tristate 4ma output pad buffer with slew rate control. table 24. general interface electrical characteristics parameter conditions min typ max unit iil low level input current vi=0v 1 m a iih high level input current vi=vcc 1 m a ioz tri-state output leakage 1 <1>the leakage currents are generally very small, < 1na. the value given here, 1ma, is a maximum that can occur after an esd stress. vo=0v or vcc 1 m a table 25. cmos output pad (bt4cr) dc electrical characteristics 1 , 2 <1>characterized for vcc=3.0 to 3.6v. this pad must be characterized at vcc=5.0v+-5% and the table updated <2>assumes a 200mv voltage drop in both supply lines. this will not be the case in the STLC1511. parameter conditions min typ max unit vol low level output voltage iol=4ma 0.4 v voh high level output voltage ioh=4ma 0.9*vdd5 vdd5 v table 26. ttl input pad (tlcht) dc electrical characteristics 1 , 2 <1>characterized for vcc=3.0 to 3.6v. this pad must be characterized at vcc=5.0v+-5% and the table updated <2>assumes a 200mv voltage drop in both supply lines. this will not be the case in the STLC1511. parameter conditions min typ max unit vil low level input voltage 0.8 v vih high level input voltage 2.0 v vilhyst low level threshold input falling 0.9 1.45 v vihyst high level threshold input rising 1.4 1.9 v STLC1511 30/31 4.7 package the STLC1511 will be packaged in a 64pin 10x10x1.4mm thin quad flat pack (tqfp) package. tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 31/31 STLC1511 |
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